DESIGN OF SYNCHRONOUS COUNTER
USING JK FLIP-FLOP
Table 15. Activation table
Q Qn J K
0 --> 0 0 X
0 --> 1 1 X
1 --> 0 X 1
1 --> 1 X 0
Since there are eight states, the number of flip-flops required would be three. Now we want to implement the counter design using JK flip-flops.
Next step is to develop an excitation table from the state table, which is shown in Table 16.
Table 16. Excitation table
present state Next state flip-flop inputsQ2Q1Q0 Q2Q1Q0 J2 K2 J1 K1 JO KO
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1
Now transfer the JK states of the flip-flop inputs from the excitation table to Karnaugh maps to derive a simplified Boolean expression for each flip-flop input. This is shown in Figure 20.
Figure 20: Karnaugh map
The 1s in the Karnaugh maps of Figure 20 are grouped with "don't cares" and the following expressions for the J and K inputs of each flip-flop are obtained:
J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q1*Q0
DESIGN COUNTER USING T FLIP-FLOP
The state table will be the same as in Example 1.5.
Table : Activation table
Q Qn T
0 --> 0 0
0 --> 1 1
1 --> 0 1
1 --> 1 0
Now derive the excitation table from the state table, which is shown in Table 17.
Table 17. Excitation table.
present state Next state flip-flop inputs
Q2Q1Q0 Q2Q1Q0 T2 T1 T0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
Next step is to transfer the flip-flop input functions to Karnaugh maps to derive a simplified Boolean expressions, which is shown in Figure 23.
Figure 23. Karnaugh maps
The following expressions are obtained:
T0 = 1; T1 = Q0; T2 = Q1*Q0
Finally, draw the logic diagram of the circuit from the expressions obtained. The complete logic diagram of the counter is shown in Figure 24.
Figure 24. Logic diagram of 3-bit binary counter.
